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1 ia3223/3222-ds rev 4.2r 0607 www.silabs.com/integration functional block diagram isobridge ? isobridge ? ia3222/ia3223 package options extclk 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sclk cs # d in d out rx out tx in ac ref ict v ss icr v dd icg linestat c ext 2 c ext 1 hook 1 2 3 4 10 9 8 7 ict icr icg v dd gnd ac in cx 5 6 hcap cx1 hook 1 2 3 4 8 7 6 5 ict icr icg v dd gnd ac in hcap extclk 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 sclk cs# d in d out rx out tx in ac ref ict v ss icr v dd icg linestat c ext2 c ext1 liu/ldn 9 10 rng/ppu 12 11 lp ofhk 20-pin qsop (ia3223a) 16-pin qsop (ia3223) 10-pin msop (ia3222b) 8-pin soic (ia3222a) see back page for ordering information. ia3222 / ia3223 ez daa ? chipset with analog interface description the ia3222 and ia3223 integrated v. 92 (56k) capable data access arrangement (daa) chipset is suitable for worldwide telephone line interface requirements and standards. the patented isobridge tm isolation t echnology eliminates the need for usual telecom isolation components, such as transformers or optocouplers. innovative techniques reduce the overall number of discrete components, thus reducing the cost of the overall function. the chipset can be programmed by software to pass ptt certification worldwide. the integrated v.92 ez daa tm offers an easy-to-use analo g interface with an internal or external dc reference for interfacing to a variety of systems seamlessly. it allows easy building-block integration where audio codecs are either separate or integrated into dsps. it is also ideal for non- modem systems requiring isolated daas, such as alarm systems, voip and pbx fxo interfaces, etc. u.s. patents #7,031,458 and #7,139,391 features ? programmable worldwide telecom compliance with one hardware build ? v.92 (56kb/s) performance ? virtually unlimited high-voltage isolation ? highly competitive bom cost ? lowest pin count (26) chipset ? high common-mode rf immunity without costly filtering ? continuous dc & audio snooping with >5m ? tip to ring ? parallel pick-up, line-in-use, ring, and ?911? detection ? -86dbm receiver noise floor ? +6dbm transmit power ? micropower line-side device powered from line ? 120db caller id common-mode rejection at 120hz typical applications ? fax-engine transformer da a lower-cost retrofits ? integrated modems ? set-top boxes ? point-of-sale terminals ? metering devices ? card readers ? alarm systems ? pbx fxo/ip telephony
ia3222/ia3223 2 table of contents functional bloc k diag ram....................................................................................................... .........................................1 table of contents.............................................................................................................. .................................................2 table of figures ............................................................................................................... ...................................................4 overview....................................................................................................................... ...........................................................5 analog inte rface ............................................................................................................... ............................................................5 isolation barrier .............................................................................................................. ..............................................................5 international compli ance....................................................................................................... .......................................................5 serial in terface ............................................................................................................... ..............................................................5 international progr amming se quence ............................................................................................. .............................................5 hook co ntrol ................................................................................................................... ..............................................................5 line overload protec tion....................................................................................................... .......................................................5 dc termination (voltage drop vs. loop current) ................................................................................. .......................................5 ac termination (line impedance matchi ng) ....................................................................................... .........................................6 dtmf dia ling ................................................................................................................... ............................................................6 pulse di aling .................................................................................................................. ..............................................................6 caller id ...................................................................................................................... .................................................................6 power-dow n m ode................................................................................................................ .......................................................6 package pin de finitions........................................................................................................ .............................................7 ia3223 system si de (qso p-16) ................................................................................................... ...............................................7 ia3223a system side (qso p-20) .................................................................................................. .............................................8 ia3222a line si de (soic -8) ..................................................................................................... ...................................................9 ia3222b line si de (msop -10) .................................................................................................... ................................................9 electrical spec ifications...................................................................................................... ........................................10 absolute maxi mum rati ngs....................................................................................................... .................................................10 recommended operat ing cond itions ............................................................................................... .........................................10 dc characte ristics ............................................................................................................. ........................................................11 ac characte ristics............................................................................................................. .........................................................11 off-hook receiver performance .................................................................................................. ..............................................12 on-hook receiver (caller id) performance at 48v dc ................................................................................................................12 transmitter pe rform ance........................................................................................................ ....................................................13 line-side char acterist ics ...................................................................................................... .....................................................14 typical perform ance graphs..................................................................................................... ..................................15 registe rs ...................................................................................................................... ........................................................19 register map................................................................................................................... ...........................................................19 control re gister ............................................................................................................... ..........................................................19 line-side progra mming regi sters ................................................................................................ .............................................19 threshold regist er ............................................................................................................. ........................................................20 line status regist er (read only)............................................................................................... ................................................20 divider re gister............................................................................................................... ...........................................................21 applications ................................................................................................................... .....................................................22 application schemat ic .......................................................................................................... ......................................................22 bill of ma terials .............................................................................................................. .............................................................23 application schematic (legacy tbr21 current-lim it support)..................................................................... .............................24 bill of materials (legacy tb r21 current-lim it s upport) ......................................................................... ....................................25 component discussion ........................................................................................................... ...................................................26 sample layout .................................................................................................................. .........................................................27 layout gu ideli nes .............................................................................................................. ........................................................27 interfacing the ia 3223 ......................................................................................................... .......................................................28 interfacing exampl es........................................................................................................... .......................................................29 line moni toring................................................................................................................ ...................................................30 theory of operation? on-hook li ne stat us........................................................................................ .......................................30 ringing ........................................................................................................................ ...............................................................30
ia3222/ia3223 3 line re versal .................................................................................................................. ...........................................................31 line ac tivity .................................................................................................................. ..............................................................31 line in use and line disco nnect ................................................................................................ ................................................32 the linestat pin as in terrupt (o n hook ) ........................................................................................ ............................................32 audio sn ooping................................................................................................................. .........................................................32 theory of operation? off-hook line status...................................................................................... ........................................32 line drop...................................................................................................................... ..............................................................33 parallel pickup ................................................................................................................ ...........................................................33 the linestat pin as in terrupt ( off hook) ....................................................................................... .............................................33 measuring loop-current changes th rough the received audio signal............................................................... .......................34 surges, isolat ion and emc ...................................................................................................... .......................................35 safety isolation and differentia l surg es ....................................................................................... ..............................................35 power-line cross............................................................................................................... ........................................................37 common-mode noise from the main s supply........................................................................................ ....................................38 emc ............................................................................................................................ ...............................................................39 rf suscept ibility .............................................................................................................. ..........................................................39 return loss and trans- hybrid ret urn loss ....................................................................................... ...................40 package information ............................................................................................................ ...........................................42 qsop-16 and qsop -20 pa ckages................................................................................................... .........................................42 msop-10 package................................................................................................................ .....................................................42 soic-8 package (jedec outline ms-012aa) ...........................................................................................................................42 ordering in formation........................................................................................................... ...........................................43
ia3222/ia3223 4 table of figures figure 1: serial interface write-cycle ti ming diagram (data ou tput pin fl oating)............................................... .................................. 10 figure 2: serial interface read-cycle timi ng diagram........................................................................... ................................................. 11 figure 3: transmit gain with resistive loads................................................................................... ....................................................... 15 figure 4: transmit gain with complex loads..................................................................................... ..................................................... 15 figure 5: transmit gain at high frequencies, 600 ? ............................................................................................................................. 15 figure 6: receive gain versus fr equency ........................................................................................ ...................................................... 15 figure 7: receive gain at high frequencies, 600 ? .............................................................................................................................. 1 5 figure 8: snoop gain versus frequency.......................................................................................... ....................................................... 15 figure 9: snoop gain ve rsus line dc voltage .................................................................................... .................................................... 16 figure 10: snoop noise ve rsus line dc voltage .................................................................................. .................................................. 16 figure 11: dc voltage vers us current, no regulation ............................................................................ ................................................ 16 figure 12: dc voltage versus current, tbr21 regulation......................................................................... ............................................ 16 figure 13: return loss for resistiv e modes ..................................................................................... ...................................................... 16 figure 14: return lo ss for comple x modes ....................................................................................... .................................................... 16 figure 15: trans-hybrid lo ss for resist ive modes............................................................................... ................................................... 17 figure 16: trans-hybrid loss for comp lex modes................................................................................. ................................................. 17 figure 17: trans-hybrid loss in 600 ? mode with va rious loads....................................................................................................... .... 17 figure 18: current-sensor ga in versus te mperatur e s ............................................................................ ............................................. 17 figure 19: parallel-pickup sensit ivity to transm itted signals .................................................................. ............................................. 17 figure 20: transmitter-path psr aliasing into au dio band with selected out-of-band fr equencies................................. .................. 17 figure 21: receiver-path psr aliasing into audi o band with selected ou t-of-band fr equencies .................................... ................... 18 figure 22: aliasing into audio band (signals at sele cted out-of-band frequencie s injected in to tx pin.......................... ................... 18 figure 23: transmitter-path cmr aliasing into au dio band with selected out-of-band fr equencies................................. ................. 18 figure 24: receiver out-of-ban d spurs.......................................................................................... ........................................................ 18 figure 21: rf immunity , iec61000-4- 6 method .................................................................................... .............................................. 18 figure 22: transmit gain versus acin capaci tor................................................................................. .................................................. 18 figure 23: applic ation schematic ............................................................................................... ........................................................... 22 figure 24: application schematic for legacy tbr21 current -limit support ........................................................ .................................. 24 figure 25: ia3222/3223 evaluation board ........................................................................................ .................................................. 26 figure 26: ia3222/3223 eval uation boar d layo ut ................................................................................. .............................................. 27 figure 27: single-e nded interface .............................................................................................. ........................................................... 29 figure 28: differential inte rface ? withou t reference .......................................................................... ................................................ 29 figure 29: differential inte rface ? with reference............................................................................. ................................................... 29
ia3222/ia3223 5 overview the chipset provides, in an integrated solution, a low-cost worldwide compliant telephone line interface. due to its high level of integration, only a few external components are required for operation. its patented isobridge ? technology eliminates the need for costly and bulky transformers, yet still insuring a high level of isolation between the phone line and the system side. analog interface the daa is easily interfaced using single-ended transmitters and receivers. an extra input pin can be used to set the dc reference, thus facilitating the interfacing with or without coupling capacitors. refer to th e applications section below for more details. isolation barrier in most cases, equipment meant to be connected to the public switch telephone network must comply with specific safety requirements, including the impl ementation of a high-voltage isolation barrier between the telephone line side and the system side. various standards re quire the isolation barrier to withstand from 1000v ac to 3000v ac . the chipset implements a high-voltage isolation barrier between the ia3223 codec and its ia3222 line-side device by mean s of its patented isobridge technology. where typical desi gns use costly transformers, optocouplers or discrete high voltage capacitors, isobridge reduces the bill of materials total cost by embedding high voltage capacitors into the pcb. this unique technique allows for virtually zero-cost capacitors. pcb board material and thickn ess, trace width and pads dimensions determine the capacitance achieved by this technique. the ia3222/ia3223 requires three 0.7pf (nominal) capacitors to operate. the chipse t is designed to operate over the wide variation range seen in standard pcb materials. the application requires only three pcb capacitors, whose diameters range typically from 140 to 190 mils, depending on the thickness of the board. international compliance the chipset can be programmed to meet all the variety of telecommunication requirements and standards worldwide through the serial loading of two registers. serial interface the ia3222/ia3223 can be programmed using a simple asynchronous serial protocol. programming the daa registers is asynchronous and independent of the data path. when cs# is low (active), the first clock rising edge latches the read or write command. the next three clock edges latch a three-bit register address. the next four clock rising edges serially shift a four-bit data word in, or the next four clock falling edges serially shift a four-bit data word out, depending on the status of the read/write command. refer to the timing diagrams in the specification section for more details on the serial interface. international programming sequence international programming option s are loaded into the system side and updated to the line si de upon three possible events: ? upon register loading if the line side is in the off-hook state ? when the line side is made to go off hook ? when the line side recovers from a line interruption hook control the daa is set on hook and off hook by writing a bit in a register through the serial interface. line overload protection the chipset provides a built-in line-overload protection circuit to protect the ia3222 line-side device from unusual telephone line conditions, which could result in excessive voltage or current conditions. if the ia3222 senses an excessive line voltage (about 100v) when on hook, it will not go off hook even when an off-hook state is set in the control register. if the ia3222 senses an excessive loop current (about 170ma) when off hook, it will immediately go on hook. this will result in oscillation since in this case the ia3222 still sees an off-hook command and therefore keeps trying to go back off hook. while a fault condition exists, the ld status bit is high. dc termination (voltage drop vs. loop current) the chipset offers four main dc termination modes and line- current limiting support specific for legacy tbr21 countries. since tbr21 has been superseded by es 203 021, european countries no longer rely on current limitation. while the ia3222/3223 chipset supports this mode for the few remaining countries that may still require current limiting, this requirement is expected to disappe ar rapidly. the four main dc headroom modes ensure that any country voltage-drop requirement can be met. the maximum transmitted level is different for each setting. pcb board isobridge cap tm top l ayer bottom layer
ia3222/ia3223 6 ac termination (line impedance matching) the chipset offers several different ac impedance terminations selectable through the serial port. these ac impedances can be combined with any dc termination selected to address a country?s loop or trunk interface requirements. refer to the section ?return loss and trans-hybrid return loss? for more details. dtmf dialing dtmf dialing is synthesized and generated by the application; only a few parameters in the ia3223, such as the gain and maximum transmission level, need to be set prior to dialing. pulse dialing pulse dialing is accomplished by going on hook and off hook repeatedly to generate the make and break pulses. it is the system application?s responsibili ty to implement the different timings related to the pulse dialing specification, such as make/break times and ratio, inter-digit pause and pulses per second settings depending on the intended country ?s specification. the ia3222 meets pulse-dialing overshoot requirements on inductive lines for australia and a few other countries. caller id when the device is on hook, the caller id audio signal is available at the receiver output pin of the ia3223. this function is achieved while maintaining the high on-hook impedance required by telecom regulations. the gain can be set high (0 db) for normal operation or low (-6 db) for dtmf monitoring. power-down mode in order to reduce power consumption, it is possible to set the ia3223 to power-down mode. in this state the device may not go off hook or monitor the line.
ia3222/ia3223 7 package pin definitions pin-type key: d=digital, a=analog, s=supply, i=input, o=output, io=input/output pu=weak internal pull-up resistor pd=weak internal pull-down resistor ia3223 system side (qsop-16) ia3223 system side pin definitions pin number pin name pin type pin function 1 linestat do, pu line status open-drain output [see note.] 2 sclk di serial interface clock 3 cs# di serial interface chip select, active low with weak pull-down 4 d in di serial interface data in 5 d out do serial interface data out 6 tx in ai daa transmit input 7 rx out ao daa receive output 8 extclk di, pd optional external clock; this pin may be left open. 9 c ext2 aio external capacitor #2 connection 10 c ext1 aio external capacitor #1 connection 11 ac ref ai daa optional dc offset; this pin may be left open. 12 icg aio line-side isobridge interface reference ground 13 v dd s positive power supply 14 icr ai line-side isobridge interface for receiver path 15 v ss s system ground 16 ict ao line-side isobridge in terface for transmitter path note: refer to the section on line monitoring for a description of the line-status pin. extclk 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sclk cs # d in d out rx out tx in ac ref ict v ss icr v dd icg linestat c ext 2 c ext 1
ia3222/ia3223 8 ia3223a system side (qsop-20) ia3223 system side pin definitions pin number pin name pin type pin function 1 linestat do, pu line status open-drain output [see note.] 2 sclk di serial interface clock 3 cs# di serial interface chip select, active low with weak pull-down 4 d in di serial interface data in 5 d out do serial interface data out 6 tx in ai daa transmit input 7 rx out ao daa receive output 8 extclk di, pd optional external clock; this pin may be left open. 9 rng/ppu do ring signal (on h ook) or parallel pickup (off hook) 10 liu/ld do line in use or disc onnect (on hook) or line drop (off hook) 11 lp do line polarity (on hook and off hook) 12 ofhk di, pd off hook, active high, ored with internal ofh control bit 13 c ext2 aio external capacitor #2 connection 14 c ext1 aio external capacitor #1 connection 15 ac ref ai daa optional dc offset; this pin may be left open. 16 icg aio line-side isobridge interface reference ground 17 v dd s positive power supply 18 icr ai line-side isobridge interface for receiver path 19 v ss s system ground 20 ict ao line-side isobridge in terface for transmitter path note: refer to the section on line monitoring for a description of the line-status pin. extclk 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 sclk cs # d in d out rx out tx in ac ref ict v ss icr v dd icg linestat c ext 2 c ext 1 liu/ldn 9 10 rng/ppu 12 11 lp ofhk
ia3222/ia3223 9 ia3222a line side (soic-8) ia3222a line side pin definitions pin number pin name pin function 1 hook hook-switch control 2 ict line-side isobridge tm interface for transmitter path 3 icr line-side isobridge tm interface for receiver path 4 icg line-side isobridge tm interface reference ground 5 hcap holding capacitor connection 6 ac in receiver path sensing capacitor input 7 gnd device ground 8 v dd device supply, self regulat ed through hook-switch transistor ia3222b line side (msop-10) ia3222b line side pin definitions pin number pin name pin function 1 hook hook-switch control 2 ict line-side isobridge tm interface for transmitter path 3 icr line-side isobridge tm interface for receiver path 4 icg line-side isobridge tm interface reference ground 5 hcap holding capacitor connection 6 c x1 termination-impedance capacitor 7 c x termination-impedance capacitor 8 ac in receiver path sensing capacitor input 9 gnd device ground 10 v dd device supply, self regulat ed through hook-switch transistor
ia3222/ia3223 10 electrical specifications absolute maximum ratings parameter minimum maximum unit junction operating and storage temperature -40 150 oc esd (human body model) 2 kv power-supply voltage -0.5 7 v voltage at any pin -0.5 v dd + 0.5 v current at any input or output (system side) -100 100 ma loop current (ia3222) 150 ma recommended operating conditions symbol parameter min. typ. max. unit operating temperature -25 85 oc vdd power-supply voltage 3.0 3.3 3.6 v vil logic low input voltage 0 35 % v dd vih logic high input voltage 65 100 % v dd v acref optional ac ref pin reference voltage (see note) 1.2 1.8 v ac reference capacitor (pin left open ? see note) 100 nf c1 external capacitor #1 10 nf c2 external capacitor #2 220 nf rx out load resistance 2 k ? rx out load ca p acitance 200 pf loop current 20 120 ma loop current, degraded performance 14 130 ma line voltage for caller id power 15 70 v internal sampling rate based on external clock 57.6 83.333 khz tck serial clock period 25 note: the ac ref pin may be left open, in which case this internal bias voltage needs to be decoupled to the audio ground by means of a 100nf capacitor. refer to dc characteri stics table for more information on driving the ac ref pin. clock cs# data in 0 (write) a2 a1 a0 di3 di2 di1 di0 tcssuf tcssur tdisu tdih tcsh x x clock cs# data in figure 1: serial interface write-cycle ti ming diagram (data output pin floating)
ia3222/ia3223 11 dc characteristics parameter conditions min. typ. max. unit logic input current -10 10 a logic input hysteresis 240 mv logic output low voltage i ol = -4ma 0.4 v logic output high voltage i oh = 4ma 0.8 v dd rth[1:0] = 00 10 20 v rms rth[1:0] = 01 12.5 25 v rms rth[1:0] = 10 15 30 v rms ring-detection threshold rth[1:0] = 11 20 40 v rms voltage at ac ref pin pin left open 1.42 1.50 1.58 v ac ref input resistance small signal 42 60 78 k ? ac ref input current sink or source 10 a pull-down resistance extclk, ofhk inputs, v = 0.65 vdd 80 300 k ? pull-up resistance linestat open-drain output, v = 0.35 vdd 80 300 k ? off hook, internal clock 7.9 ma off hook, external clock 6.2 ma on hook 3.4 ma power supply current power down, no external clock 2 a normal headroom, tbr21 mode 0.95 mv/ma loop-current sensor gain all other headroom and impedance modes 1.15 mv/ma ac characteristics symbol parameter min. typ. max. unit note tcdo clock falling edge to data out valid from driven or floating state 12 20 ns load = 50 pf tcsdf chip select disabled to data out floating 12 20 ns load = 50 pf internal sampling rate based on internal clock 67.2 73.4 82.8 khz clock cs# data in data out floating 1 (read) a2 a1 a0 x (don't care) floating do3 do2 do1 do0 tcdo tcsdf tcdo x clock cs# data in data out figure 2: serial interface read-cycle timing diagram
ia3222/ia3223 12 off-hook receiver performance parameter conditions min. typ. max. unit idle channel noise referred to tip and ring 300hz - 3400hz, 600 ? , internal clock -85 dbm total harmonic distortion 1khz, -7 dbm, normal or high headroom -76 db gain from tip and ring to rx out pin 1khz (symmetrical around ac ref ), high headroom -3 db gain from tip and ring to rx out pin 1khz (symmetrical around ac ref ), other headrooms 0 db sine wave, high headroom, referenced to 600 ? 0 dbm sine wave, normal headroom, referenced to 600 ? -3 dbm sine wave, low headroom, referenced to 600 ? -3 dbm receiver power headroom sine wave, lowest headroom, referenced to 600 ? -5 dbm maximum level at rx out pin 1khz (symmetrical around ac ref ) 1.55 v pp 1khz, 100 mv pp at v dd , high headroom -84 dbv 1khz, 100 mv pp at v dd , other headrooms -87 dbv f > 3400hz, dc coupled, high headroom -66 dbv power-supply induced noise referred to tip and ring f > 3400hz, dc coupled, other headrooms -69 dbv longitudinal balance f = 1000hz 99 db longitudinal balance f = 3000hz 93 db on-hook receiver (caller id) performance at 48v dc parameter conditions min. typ. max. unit caller id noise referred to tip and ring 400hz - 3000hz, internal clock -48 dbv caller id distortion 1khz, 100 mv rms , normal or high headroom -37 db 1khz, high gain setting 0.5 db caller id gain, tip and ring to ac ref 1khz, low gain setting -4.5 db 1khz, high gain setting -3 dbm maximum level at tip and ring 1khz, low gain setting +3 dbm maximum level at rx pin 1khz, high or low gain setting 1.55 v pp 1khz, 100 mv pp at v dd , high gain setting -55 dbv power-supply induced noise referred to tip and ring 1khz, 100 mv pp at v dd , low gain setting -50 dbv common-mode rejection 120hz 120 db
ia3222/ia3223 13 transmitter performance parameter conditions min. typ. max. unit idle channel noise referred to tip and ring 300hz - 3400hz, 600 ? , internal clock -82 dbm total harmonic distortion 1khz, 3db below clipping level, normal or high headroom -78 db 1khz, 600 ? , referenced to ac ref , high headroom 9 db gain from tx in pin to tip and ring 1khz, 600 ? , referenced to ac ref , other headrooms 6 db transmitter gain 0.5 db part-to-part gain variation at 1khz, 600 ? mode, normal headroom product of transmitter gain times receiver gain 0.5 db lp[5:4]=00, 600 ? load +6.5 dbm lp[5:4]=00, 900 ? load +5.5 dbv lp[5:4]=01, 600 ? load +3 dbm lp[5:4]=01, 900 ? load +2 dbv lp[5:4]=01, australia or tbr21 load +2 dbv lp[5:4]=01, new zealand load +1 dbv lp[5:4]=10, 600 ? load, 400-3400 hz -5 dbm lp[5:4]=10, 600 ? load with bootstrap, 400-3400 hz -1 dbm lp[5:4]=11, 600 ? load, 400-3400 hz -9 dbm lp[5:4]=11, 600 ? load with bootstrap, 400-3400 hz -3 dbm transmitter power headroom, sine wave (see note.) lp[5:4]=11, 600 ? load with bootstrap, dtmf tones -1 dbm tx in pin input resistance 35 50 65 k ? 300hz - 3400hz, dc coupled 40 db input common-mode rejection, defined as ( v(tx in ) + v(ac ref ) ) / 2 f > 3400hz, dc coupled 40 db 1khz, 100 mv pp at v dd , high headroom -86 dbv 1khz, 100 mv pp at v dd , other headrooms -89 dbv f > 3400hz, dc coupled, high headroom -56 dbv power-supply induced noise referred to tip and ring (sgain = 0) f > 3400hz, dc coupled, other headrooms -59 dbv longitudinal balance f = 1000hz or f = 3000hz 90 db note: the bootstrap circuit shown in the application circuit (r18, c16 and q6) is optional. its function is to increase the transmit headroom voltage at the low and lowest headroom settings. th ose settings should be used only when the dc voltage needs to be minimized for low-voltage countries such as japan, malaysia, etc.
ia3222/ia3223 14 line-side characteristics parameter conditions min. typ. max. unit self-regulated supply voltage 2.47 v current protection threshold 130 170 210 ma on-hook voltage-protection threshold 80 108 135 v temperature-shutdown threshold loop current = 130 ma 136 146 156 oc on-hook dc resistance, tip to ring 5.6 m ? voltage-sensing resistors 5 m ? ringer equivalent load 0.1 ren 600 ? impedance mode and reference load 20 30 db 600 ? + 1 f impedance mode and reference load 20 30 db 900 ? impedance mode and reference load 20 30 db 900 ? + 1 f impedance mode and reference load 20 30 db australia impedance mode and reference load 17 27 db new zealand impedance mode and reference load 20 26 db return loss at 1 khz (typical) or 300 ? 3400 hz (minimum) tbr21 impedance mode and reference load 17 27 db 600 ? impedance mode and reference load 20 30 db 600 ? + 1 f impedance mode and reference load 20 30 db 900 ? impedance mode and reference load 20 30 db 900 ? + 1 f impedance mode and reference load 20 28 db australia impedance mode and reference load 20 25 db new zealand impedance mode and reference load 20 26 db echo return loss, itu-t g.122 method tbr21 impedance mode and reference load 20 25 db trans-hybrid distortion referred to line 600 ? load, -10 dbm signal, normal or high headroom -91 dbm i dd = 20ma, no current limit, lowest headroom 5.85 6 v i dd = 20ma, no current limit, low headroom 6.4 7 v i dd = 20ma, no current limit, normal headroom 7.8 9 v i dd = 20ma, no current limit, high headroom 9 10 v i dd = 42ma, tbr21 current limit, normal headroom 14.5 v tip-ring voltage i dd = 50ma, tbr21 current limit, normal headroom 40 v loop-current limit tbr21 legacy mode, 50 v, 230 ? feed 60 ma
ia3222/ia3223 15 typical performance graphs transmit gain with resistive loads versus frequency (hz) 0 1 2 3 4 5 6 0 500 1000 1500 2000 2500 3000 3500 4000 600 ? , lp[5:4]=00 900 ? , lp[5:4]=00 600 ? , lp[5:4]=01 900 ? , lp[5:4]=01 figure 3: transmit gain with resistive loads transmit gain with complex loads versus frequency (hz) 0 1 2 3 4 5 6 0 500 1000 1500 2000 2500 3000 3500 4000 aus tralia, lp[5:4]=01 new zealand, lp[5:4]=01 tbr21, lp[5:4]=01 figure 4: transmit gain with complex loads transmit gain at high frequencies, 64 ks/s -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 frequency (khz) gain (db) figure 5: transmit gain at high frequencies, 600 ? receive gain versus frequency (hz) 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 0 500 1000 1500 2000 2500 3000 3500 4000 600 ? , lp[5:4]=00 600 ? , lp[5:4]=01 aus tralia, lp[5:4]=01 new zealand, lp[5:4]=01 figure 6: receive gain versus frequency receive gain at high frequencies, 64 ks/s -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728 frequency (khz) gain (db) figure 7: receive gain at high frequencies, 600 ? snoop gain versus frequency (hz) at 48 v 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 300 600 900 1200 1500 1800 low gain high gain figure 8: snoop gain versus frequency transmit gain at high frequencies, 64ks/s receive gain at high frequencies, 64ks/s
ia3222/ia3223 16 snoop gain versus dc voltage (v) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 24 30 36 42 48 54 60 low gain high gain figure 9: snoop gain versus line dc voltage snoop noise (dbv) versus dc voltage (v) -54 -53 -52 -51 -50 -49 -48 -47 -46 24 30 36 42 48 54 60 low gain high gain figure 10: snoop noise versus line dc voltage dc voltage drop (v) versus loop current (ma) 6 7 8 9 10 11 12 13 20 40 60 80 100 120 lp[5:4]=00 lp[5:4]=01 lp[5:4]=10 lp[5:4]=11 figure 11: dc voltage vers us current, no regulation voltage vs. current, tbr21 current limit 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 10 20 30 40 50 60 loop current (ma) tip-ring voltage (v) tbr21 regulation mode, normal headroom tbr21 requirement figure 12: dc voltage versus current, tbr21 regulation return loss (db) with resistive loads versus frequency (hz) 16 20 24 28 32 36 40 44 200 600 1000 1400 1800 2200 2600 3000 3400 600 ? , lp[5:4]=00 900 ? , lp[5:4]=00 900 ? , lp[5:4]=01 600 ? , lp[5:4]=11 figure 13: return loss for resistive modes return loss (db) with complex loads versus frequency (hz) 16 18 20 22 24 26 28 30 32 34 200 600 1000 1400 1800 2200 2600 3000 3400 aus tralia, lp[5:4]=01 new zealand, lp[5:4]=01 tbr21, lp[5:4]=01 figure 14: return loss for complex modes voltage vs. current, tbr21 current limit
ia3222/ia3223 17 hybrid loss (db) w ith resistive loads versus frequency (hz) -4 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 500 1000 1500 2000 2500 3000 3500 4000 600 ? , lp[5:4]=00 900 ? , lp[5:4]=01 600 ? , lp[5:4]=11 figure 15: trans-hybrid loss for resistive modes hybrid loss (db) with complex loads versus frequency (hz) -4 0 4 8 12 16 20 24 28 32 36 40 0 500 1000 1500 2000 2500 3000 3500 4000 aus tralia, lp[5:4]=01 new zealand, lp[5:4]=01 tbr21, lp[5:4]=01 figure 16: trans-hybrid loss for complex modes trans-hybrid loss in 600 ? mode with various loads -5 0 5 10 15 20 25 30 35 40 10 100 1000 10000 frequency (hz) loss at 600 ? load (db) loss at 900 ? load (db) loss with austel load (db) figure 17: trans-hybrid loss in 600 ? mode with various loads current-sensor gain versus temperature 1.05 1.1 1.15 1.2 1.25 -30-20-10 0 102030405060708090100 temperature (c) gain (mv/ma) figure 18: current-sensor gain versus temperature s parallel-pickup circuit sensitivity to transmitted signal -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 0 50 100 150 200 250 300 350 400 frequency (hz) transmitted signal (dbv) hi hdrm, th=0 hi hdrm, th=1 hi hdrm, th=2 hi hdrm, th=3 lo hdrm, th=0 lo hdrm, th=1 lo hdrm, th=2 lo hdrm, th=3 figure 19: parallel-pickup sensi tivity to transmitted signals transmitter-path psr aliasing into audio band with selected out-of-band frequencies -50 -48 -46 -44 -42 -40 -38 -36 -34 -32 -30 10 100 1000 10000 100000 frequency (khz) rejection (db) external clock (khz) 64 internal clock (khz) 73.4313 figure 20: transmitter-path psr aliasing into audio band with selected out-of-band frequencies transmitter-path psr aliasing into audio band with selected out-of-band frequencies
ia3222/ia3223 18 receiver-path psr aliasing into audio band with selected out-of-band frequencies -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 -50 -48 -46 -44 10 100 1000 10000 100000 frequency (khz) rejec tion (db ) external clock (khz) 64 internal clock (khz) 73.4313 figure 21: receiver-path psr aliasing into audio band with selected out-of-band frequencies out-of-band frequencies aliased into the transmitter and receiver paths -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 10 100 1000 10000 100000 frequency (khz) attenuation (db ) tx out-of-band rejection hybrid out-of-band rejection figure 22: aliasing into audio band (signals at selected out-of-band frequencies injected into tx pin transmitter-path cmr aliasing into audio band w ith selected out-of-band frequencies -68.00 -66.00 -64.00 -62.00 -60.00 -58.00 -56.00 -54.00 -52.00 -50.00 -48.00 -46.00 -44.00 -42.00 -40.00 -38.00 -36.00 -34.00 10 100 1000 10000 100000 frequency (khz) rejection (db) external clock (khz) 64 internal clock (khz) 73.4313 figure 23: transmitter-path cmr aliasing into audio band with selected out-of-band frequencies receiver out-of-band spurs -72 -70 -68 -66 -64 -62 -60 -58 10000 100000 1000000 10000000 100000000 frequency (hz) dbv internal clock external clock, 1.536 mhz / 24 figure 24: receiver out-of-band spurs rf immunity, iec61000-4-6 method 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 0.1 1 10 100 frequency (mhz) vrms (measured without modulation) competitor ia3222/3223 figure 21: rf immunity, iec61000-4-6 method transmit gain over frequency (hz) versus acin capacitor 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 10 100 1000 10000 15 nf 22 nf 33 nf 47 nf 68 nf 100 nf 220 nf figure 22: transmit gain versus acin capacitor transmitter-path cmr aliasing into audio band with selected out-of-band frequencies receiver-path psr aliasing into audio band with selected out-of-band frequencies out-of-band signals aliased into the receiver and transmitter paths receiver out - of - band spurs rf immunity, iec61000 - 4 - 6method
ia3222/ia3223 19 registers register map a2 a1 a0 register d3 d2 d1 d0 0 0 0 control ofh lsr sgain pwd 0 0 1 line side programming msb lp5 lp4 lp3 lp2 0 1 0 line side programming lsb lp1 lp0 reserved revid 0 1 1 thresholds lth1 lth0 rth1 rth0 1 0 0 line status (read only) rng/ppu liu/ld lact lp 1 0 1 dividers reserved f2 f1 f0 1 1 x reserved reserved reserved reserved reserved note: revid is a read-only bit, hardwired to zero. control register control bit definition function when low function when high reset state ofh off-hook command on hook off hook, ored with ofhk pin low lsr line status ring line-status pin reflects the state of the lact status bit (inverted). line-status pin reflects the state of the rng/ppu status bit (inverted). high sgain select gain low-gain caller id normal transmit gain high-gain caller id additional 6 db of transmitter gain low pwd power down normal operation device powered down low note: refer to the section on line monitoring for a description of the line-status pin. line-side programming registers lp5 lp4 setting 0 0 high transmit voltage headroom and dc voltage drop (reset state) 0 1 normal transmit voltage headroom and dc voltage drop 1 0 low transmit voltage headroom and dc voltage drop (note) 1 1 lowest transmit voltage headroom and dc voltage drop (note) note: this mode is not allowed in 600 ? + 1f or 900 ? + 1f impedance mode. lp3 lp2 lp0 setting ia3222a ia3222b cx required? (ia3222b only) cx1 required? (ia3222b only) 0 0 0 600 ? or 600 ? + 2.16 f yes yes 0 0 1 600 ? + 1 f (note) yes yes 0 1 0 900 ? yes 0 1 1 900 ? + 1 f (note) yes yes 1 0 0 es 203 021, australia or china complex impedance yes yes 1 0 1 new zealand complex impedance yes yes yes 1 1 0 tbr21 complex impedance with current limit yes yes 1 1 1 reserved note: this mode is not allowed with low or lowest transmit voltage headroom. lp1 setting: 0, current sensor enabled; 1, current sensor disabled (recommended when current sensor is not required) the line side is programmed when any of the following conditions is fulfi lled: (1) after going from on-hook to off-hook; (2) when the line side lsb programming register is updated by the user or (3) after recovering from a loop-current interruption (line drop).
ia3222/ia3223 20 threshold register lth1 lth0 line-in-use threshold (vdc) parallel-pickup threshold 0 0 22.5 7.5 v (reset state) 0: least sensitive (reset state) 0 1 30 10v 1 1 0 15 5v 2 1 1 line-disconnect detection (~2. 5 v) 3: most sensitive note: the parallel-pickup threshold must be selected based on line usage and history. depending on the application, selecting too sensitive a threshold may falsely detect a parallel pickup in the presence of large signals. setti ng 0 or 1 is recommended for voice applications. modem applications, where transmitted levels and frequency envelopes are well controlled, may benefit from using a more sensitive setting. refer to figure 6, which indicates the sensitivity of the detection circuit for signals of different fr equencies for various settings. note that the ?high? headroom setting, (because of the reduced receiver gain), reduces the sensitivity of the parallel-pickup function by 3 db. each setting is approximately twice as sensitive as the previous setting. rth1 rth0 no-detection ring threshold (vrms) ring threshold (vrms) 0 0 10 (reset state) 20 (reset state) 0 1 12.5 25 1 0 15 30 1 1 20 40 line status register (read only) note: writing any value to this register will reset all registers to their default values. mnemonic definition applicability status when bit is low status when bit is high rng [note 1] ring signal on hook voltage below ring threshold voltage above ring threshold ppu [note 1] parallel pickup off hook no loop-current drop loop-current drop liu [note 1] line in use on hook voltage above liu threshold voltage below liu threshold ld [note 1] line drop off hook line ac tive line disconnected or line fault on hook no change in line-in-use status change in line-in-use status lact [note 2] line activity off hook no parallel-pickup event parallel-pickup event lp [note 1] line polarity on hook an d off hook line reversed line direct notes: 1. this bit is multiplexed to a di gital output pin of the ia3223a. 2. in the on-hook state, lact will become high if the line voltage change is at least 10 to 20v in either direction.
ia3222/ia3223 21 divider register f2 f1 f0 clock mode minimum input frequency (mhz) maximum input frequency (mhz) 0 0 0 internal (reset state) 0.0672 (internal) 0.0828 (internal) 0 0 1 external divided by 24 1.38 2.0 0 1 0 external divided by 32 1.84 2.667 0 1 1 external divided by 48 2.76 4.0 1 0 0 external divided by 64 3.68 5.333 1 0 1 external divided by 96 5.52 8.0 1 1 0 external divided by 128 7.37 10.667 1 1 1 external divided by 1 0.0576 0.08333 notes: 1. table represents clock frequencies typi cally used for pcm interface devices. 2. an external clock can be used to synchronize an external codec with the daa in order to avoid aliasing.
ia3222/ia3223 22 applications application schematic ia3222b for worldwide telecom compliance figure 23: application schematic
ia3222/ia3223 23 bill of materials (all resistors are 5% and capacitors 20% tolerance unless indicated otherwise.) quantity reference part 1 br1 s1zb60 1 c1 6.8nf 200v 0805 1 c2 10f 4v 2 c3, c15 100nf 16v 0603 1 c4 22nf 200v 0805 1 c5 1nf 100v 0603 3 c6, c8, c9 isobridge tm capacitors, drawn on pcb (contact iai for details.) 1 c7 33nf 100v 1206 (see note 1.) 1 c11 330nf 10v 0603 (see note 1.) 1 c12 10nf 16v 0603 1 c13 220nf 16v 0603 1 q1 mmbta92 3 q2, q3, q4 mmbta42 (see notes 2 and 3.) 1 rv1 p3100sb 2 r1, r16 5.6m 1% 1206 1 r2 47k 0603 3 r5, r6, r7 3.3 0603 (see notes 2 and 3.) 1 r9 680 1206 1 r10 220 1206 1 r12 120k 1% 0805 1 r14 4.7k 1206 1 r15 20 1% 1206 2 u1, u2 ia3222b option c16 2.2f 6.3v 0603 (only if more signal headr oom is needed at the low or lowest headroom setting) option q6 mmbta06 (only if more signal headroom is needed at the low or lowest headroom setting) option r18 4.7k 0603 (only if more signal headroom is needed at the low or lowest headroom setting) option r8 4.7 through-hole metal-oxide or other fusible resistor (only for ul 60950 or equivalent requirement) option c10 2.7nf 100v 0805 (use only if cx is required. see note 4.) option r13 10k 0805 (use only if cx is required. see note 4.) option c14 4.7nf 100v 0805 (use only if cx1 is required. see note 4.) option r17 120k 1% 0805 (use only if cx1 is required. see note 4.) note 1: for optimal audio performance, c7 and c11 should have a 250v rating and be of 1206 size. this is especially important for applications where the pcb is less than th e standard 0.062? thickness, because cerami c capacitors are slightly piezoelectric and therefore sensitive to mechanical vibrations (microphonics) . this effect is less pronounced with components of larger size and higher voltage rating. note 2: if the loop current is never more than 60 ma, q4 and r7 may be omitted and r5 and r6 may be 2.2 ohms. note 3: do not replace q2, q3, q4, r5, r6 and r7 with a single tran sistor of pzta42 type. power transistors with a higher gain- bandwidth product may be used, but they often are not cost effe ctive. refer to the component discussion for more details. note 4: c10 and c14 need to be npo if v.90 modem performance is re quired. otherwise, it is more cost effective to use x7r ceramic capacitors.
ia3222/ia3223 24 application schematic (legacy tbr21 current-limit support) tbr21 current limit is no longer in force in europe but may still be required for certain countries, e.g. algeria, bahrain, cro atia, estonia, ghana, ivory coast, lebanon, morocco and turkey. th is application is suitable for all other countries as well. figure 24: application schematic for legacy tbr21 current-limit support
ia3222/ia3223 25 bill of materials (legacy tb r21 current-limit support) (all resistors are 5% and capacitors 20% tolerance unless indicated otherwise.) quantity reference part 1 br1 s1zb60 1 c1 6.8nf 200v 0805 1 c2 10f 4v 2 c3, c15 100nf 16v 0603 1 c4 22nf 200v 0805 1 c5 1nf 100v 0603 3 c6, c8, c9 isobridge tm capacitors, drawn on pcb (contact iai for details.) 1 c7 33nf 100v 1206 (see note 1.) 1 c11 330nf 10v 0603 (see note 1.) 1 c12 10nf 16v 0603 1 c13 220nf 16v 0603 1 q1 mmbta92 1 q6 mjd340 1 rv1 p3100sb 2 r1, r16 5.6m 1% 1206 1 r2 47k 0603 3 r3, r4, r11 270 1206 1 r10 300 1206 1 r12 120k 1% 0805 1 r14 4.7k 1206 1 r15 20 1% 1206 2 u1, u2 ia3222b option c16 1f 16v 0603 (only if more signal headroom is needed at the low or lowest headroom setting) option q6 mmbta06 (only if more signal headroom is needed at the low or lowest headroom setting) option r18 4.7k 0603 (only if more signal headroom is needed at the low or lowest headroom setting) option f1 fuse (only for ul 60950 or equivalent requirement) option c10 2.7nf 100v 0805 (use only if cx is required. see note 2.) option r13 10k 0805 (use only if cx is required. see note 2.) option c14 4.7nf 100v 0805 (use only if cx1 is required. see note 2.) option r17 120k 1% 0805 (use only if cx1 is required. see note 2.) note 1: for optimal audio performance, c7 and c11 should have a 250v rating and be of 1206 size. this is especially important for applications where the pcb is less than th e standard 0.062? thickness, because cerami c capacitors are slightly piezoelectric and therefore sensitive to mechanical vibrations (microphonics) . this effect is less pronounced with components of larger size and higher voltage rating. note 2: c10 and c14 need to be npo if v.90 modem performance is re quired. otherwise, it is more cost effective to use x7r ceramic capacitors.
ia3222/ia3223 26 component discussion the application schematic (figure 23) is intended as a high-densi ty surface-mount solution. when using through-hole components, some changes may be possible in the design. please contact iai support for these issues. the main hook switch is composed of three parallel npn transi stors (q2?q4) and three emitter ballasting resistors (r5?r7). this structure is necessary when using low cost, generic 300 v telephon e application transistors in or der to keep these transistors out of their quasi-saturation region at high loop currents. with the use of qualified transistors, it is possible to reduce the transistor count on the npn hook switch but may not be cost effective or reduce board area. although 300v rated telephone hook-switch application transistors only cost pennies, they work best as switches and tend to behave poorly when operated in their linear region at currents above 20 ma, with only a few volts drop from collector to emitter. this is due to quasi-saturation effects that reduce their frequency response to only a few mhz. even the spice models for these devices designed over 30 years ago are often inad equate in these linear operating regions. if too few of these transistors are used in the hook circuit, stability issues at hi gher loop currents may occur. as an alternative, more recently designed high-voltage npn transistors in larger packages (for power dissipa tion) can be used to construct either a double or single hook switch but may easily cost more than the thr ee-parallel npn solution. without extensive characterization, iai does not recommend alternative hook-switch transistor solutions except th e one provided for legacy tbr21 support (see below). high-density ceramic capacitors can cause bo th microphonic and distortion problems due to piezoelectric effects (mechanical str ain) and voltage coefficients (changes in capaci tance with voltage). in general, the higher a ceramic?s dielectric constant, the gre ater its voltage-dependency and piezoelectric effects. the lower the voltag e rating on a ceramic capacitor, then the higher the voltage gradient across the dielectric. this means that a capacitor of lo wer voltage rating and same dielectric material will have wors e voltage distortion and el ectromechanical effects. iai has identified which capacitors are most likely to be critical with respect to these issues on the application schematic. i t is possible to use different dielectr ic material for these capacitors if the device s are physically larger and the customer can ev aluate the board for possible increased di stortion or electro mechanical effects in the end product. legacy tbr21 support is possible but not recommended since so fe w countries require it and the standard has been superseded. current limiting is now obsolescent if not obsolete. in order to meet tbr21 current limit, a daa needs to dissipate 2 w safely. in the ia3222/3223 application, about half of this power is dissipated in r3, r4, r10 and r11 and the other half in the npn transistor . figure 25: ia3222/3223 evaluation board
ia3222/ia3223 27 sample layout figure 26: ia3222/3223 evaluation board layout layout guidelines ? minimize trace lengths between u1, r1 and r15. ? disc capacitors and their connecting traces should be drawn ex actly as shown, with 4.95mm ( 195 mils) diameters, 2.5mm (98.5 mils) spacing and 10-mil traces in between on the system side on ly. all dimensions must match. this assumes a standard board thickness (0.062?) and fr-4 material. contact iai for other board thicknesses or materials. ? carefully observe the required creepage distan ce (surface distance over isolation) for surge rating. there must be at least 2.5 mm (98.5 mils) between any line-side conductive trace and any system-side conductive trac e, including the mounting holes if the ar e electrically connected. because of pcb ma nufacturing tolerances, the minimum drawn di stances should be about 2% larger, or 2.55mm (100.5 mils). it is a good practice to designate a ?pre ferred arc path? between the tip an d ring lines and the chassis, e.g. at the rj-11 connector, by drawing those at the minimum requir ed distance, while all other spacings between line side and system side are drawn lightly larger, e.g. 2.8mm (110 mils). ? put no metal markings in the area of the disk capacitors. this must be watched closely, sinc e pcb manufacturers routinely add markings wherever they find it convenient , possibly shortening the creepage distance. ? for optimal audio performance, minimize trace lengths betw een the system side and its supply-decoupling capacitors. ? q2, q3 and q4 should be laid out with a lot of extra copper on both sides of the board with ther mal vias in order to facilitate heat dissipation.
ia3222/ia3223 28 interfacing the ia3223 the simplified block diagram below shows single ended interfac e to a/d and d/a. the analog interface consists of 3 pins: ? tx ? audio input ? rx ? audio output ? acref ? ac voltage reference there are two ways to interface to a/d and d/a: dc coupling all three pins tx, rx and acref are connected to the codec dire ctly. the acref pin has a weak internal buffer (refer to dc characteristics table), which can be overdriv en easily with an external reference. th e external reference voltage must be in th e 1.2v to 1.8v range. connecting the codec?s ac reference to the acref pin will insure good common mode rejection. one of the advantages of dc coupling is an alternative way for the host processor to detect parallel pick-up (ppu). ppu may be detected using linestat pin, as described in the next section. the alternative way is to monitor the dc offset at the rx pin. ( line- side programming bit lp1 must be set to zero.) the dc loop current is added to the rx signal as a dc offset with a gain of abou t 1 mv/ma. applying a digital low-pass filter to the rx channel audio enables the detection of a drop in the dc loop current, thus indicating a ppu event. ac coupling all three pins tx, rx and acref may also be connected to codec using coupling capacitors. for th e acref pin, a capacitor of at least 100nf is recommended. all coupling capacitors should be selected so that they will no t cause any significant attenuation at low frequencies, taking input resistances into account. the tx pin is internally biased at 1.5v. please contact silicon labs for additional assistance with interfacing the ia3223.
ia3222/ia3223 29 interfacing examples figure 27: single-ended interface 2k acref rx- tx rx tx + + - + - 2k + - + - ia3223 codec rx+ tx - figure 28: differential interface ? without reference figure 29: differential interface ? with reference from pwm converter (ac or dc coupled) (ac or dc coupled) tx (ac or dc coupled) optional codec reference 1.5v reference + - a cre f to pwm converter codec tx rx codec rx 100nf transmitter hpf + - 60k + - ia3223 + - receiver lpf 0.6v reference 3.0v reference + - codec ia3223 + - + - rx 100nf a cre f tx+ tx tx- a cre f + - + - rx+ rx-
ia3222/ia3223 30 line monitoring theory of operation?on-hook line status the ia3222/3223 chipset was designed to provide maximum info rmation about the telephone line?both ac and dc?to allow intelligent line management, and to allow automatic telephone devices to share the line with human-controlled applications gracefully. automatic daa applications may be found in set-to p boxes, alarm systems, fax machines, meter readers, remote- diagnostic modems, answering machines, voip boxes, etc. a key feature of the ia3223 is the linestat pin, which can be programme d to generate an interrupt if the line status changes either whil e in the on-hook state or in the off-hook state. this reduces th e need for continuous polling of the line-status bits. in the on-hook state, the ia3222 line side chip converts the line voltage to a frequency at the rate of 2 khz per volt. the v-t o-f?s operating range is from 3v to over 150v. this frequency is sent as pulses across the capacitor isolation barrier. the pulse d uty cycle contains line-polarity information. th e v-to-f converter?s frequency is sufficie nt to allow the ia3223 system side to dec ode all dc line voltage, ring signals, line reversals and audio inform ation (caller id, dtmf, and other tone monitoring). while monitor ing the line in the on-hook state, the line side loads the line with no less than 5 m ? dc resistance. this allows continuous monitoring while exceeding regulatory minimum idle -line resistance requirements. the ia3223 system side chip receives the frequency-encoded voltage information and converts it back to continuous representatio n of the line voltage. the voltage difference between the acref pi n and the cext2 pin is about 1/200th of the line voltage. since the dc source resistance of cext2 is about 75 k ? , any measurement system resistance should exceed 10 m ? to prevent excessive loading. for the on-hook snoop function, cext1 is part of a gyrator circui t that separates the large dc line voltage from the low-level ac voltage, so that the line audio signal may be amplified without excessive offset. cext1 sets the low-frequency corner on this g yrator circuit inversely proportional to its value. with 10 nf, the -3 db corner is around 240 hz and the slope is 6 db per octave. th e upper- frequency corner is around 4 khz. it is set by internal rc valu es, and is therefore not adjustable by the user. the upper-frequ ency roll-off exceeds 18 db per octave. in the on-hook state, cext2 filters the line voltage analog with a time constant of cext2 times 75 k ? , for separating the ac ring signal from the dc line voltage. with a cext2 of 220 nf, the corner frequency is about 10 hz. the ring-detection circuit compares the voltage on cext2 with an internal unfiltered signal. if it exce eds one of the four programmable thresholds in one direction, a ring- detection condition occurs. this produces a standard half-wave ring-detection signal th at works similarly to a standard opto-is olator ring-detection circuit. in addition to ring detection, the other on-hook functions are a line-polarity (lp) detector, a line-in-use detector (liu) and a line- activity (lact) detector. the liu detector measures if the line voltage exceeds one of four programmed voltage levels. the lact detector output is activated if the line voltage changes by more than 10 to 20v, thus acting like a sensitive full-wave ring de tector. all of these signals can be read from ia3223 regi sters. depending on the setting of the lsr bit, either the ring-detection signal o r the lact signal can be output to the linestat (line status) pin. ringing the iai 3223 supports conventional ring-detecti on algorithms that produce an on-off digi tal output when the ac signal exceeds a preset threshold. the period between cycles is measured by the system firmware to within 1-2ms to allow qualification of ring c ycles in order to differentiate them from other li ne signals: notably on-/off-h ook transients, dial pulses and test signals sent by t he telephone company. the ring-detection state is presented on read -only register rng bit and may op tionally be multiplexed to the linestat pin. the width of the ring-detection pulse is always at least 20 % of the ring period for sine-wave ring signals. many regulatory ring requirements have disappeared in the last fifteen years and the usage of pulse dialing has also decreased. in more ancient telephone history, when telephone companies were monopolies, 10 v rms signals were sent down telephone lines in order to determine how many ringer loads were present. although this probably no longer occurs, conventional wisdom is that rin g detectors should not trip below 10 v rms . many country-specific regulations and eia/tia recommendations support this requirement to this day.
ia3222/ia3223 31 the most common spurious ring detection is due to pulse dialing. in japan, 20 pulses per second used to be common. the simple way to prevent spurious ring detection from dial pulses is to set a sufficiently high ring-detec tion threshold. in countries th at have strong ring signals, setting one of the upper two thresholds (22.5 or 30 v rms ) will prevent ring detection of most of the dial pulses. the first pulse may still be detected, because the initial dial pu lse or off hook transient may pr esent a large signal to the r ing- detection circuit. subsequent dial pulses will fall below the ri ng threshold as the dc-averaging circuit centers the ac wavefor m. this problem can be seen with all conventional ring detectors. this is why ring-detection algorithms always need to qualify at least two ring cycles by ensuring they fall within the time li mits that correspond to the possible ring frequency. in some countries (e.g., the uk and australia), low ring thresholds are desired. rather than setting parameters of ring thresho ld, period, and number of valid cycles for each and every country, it is simpler to divi de the whole world into a few separate ring qualification groups. valid ring signals ar e between 15 and 68 hz. ring cadences are ne ver more than 2 seconds on but may be as little as 0.2 seconds for distinctive ringin g. if a 1ms period resolution is availabl e, and assuming a tolerance of 10 % 1 ms , the valid period range is 12 to 74 ms. these period limits screen out 10 pps but not 20 pps pulse dial ers. an example of two ring qualifier groups would thus be: ? set lowest ring threshold (15 v rms ), qualify ring period 12 to 74 ms, require at leas t two to three valid periods in a row (disqualify if any period falls outside this range). this wo rks worldwide except for 20 pps pulse dialing. ? for strong ringer countries (e.g., north america and japan) , use the same criteria but set the ring threshold to 30 v rms . line reversal (lr), line in use (liu), or line activity (lact) may also be used for ring detection in limited circumstances. li ne reversal is probably safe in high ringer -threshold countries and would re ject 20 pps dial pulses effectiv ely. in low ringer-threshold co untries, it may not reliably detect weak ring signals since the ringer signal typically rides on top of the dc line voltage. if the ringer ac peaks are less than the line voltage, line reversal will not occur. lact and liu will almost always be triggered on any ring signal but qualifying the ring frequency is a problem because both det ectors may produce more than one pulse per ring period. although lact is a sensitive full-wave ring detector, full-wave ring detectors are less accurate with period because ring signals can be asymmetric either because of origination or because of loading. in additi on, the lact detector is not as precise as the ring detector. its threshold may vary from 10 to 20v peak. another ring-detection scheme makes use of the snoop audio output available at the rxou t pin. if the -6 db snoop gain is set (s gain bit set to zero) and if the cext1 corner is placed correctly, the ring signal will be available in the snoop audio path with su fficient attenuation to avoid clipping. a cext1 of 10 nf will work well for typical 20 hz ring signals. if the ring signal is expected t o be around 50 hz, cext1 should be reduced to 4.7 nf. this will increase the -3 db high-pass corner of the snoop audio path to about 700 hz , which is normally acceptable for caller id signals. line reversal on-hook line reversal (not to be confused with off-hook loop current reversal) occurs in some countries instead of the first ri ng cadence before the caller id message. line reversal may also be used for other signaling. typically, many daas with line-revers al detection capability can only detect the transient and not the ac tual line polarity, making it difficult to differentiate a lin e reversal from an off hook transient. the ia3223 has a true line-polarity detector. line polari ty is directly sensed in the ia3222 line-s ide chip and this information is sent across the isolation barrier to th e ia3223 system-side chip. line pola rity reversal may take up to 50 ms. through this transition all three detectors li ne in use, line activity, and ring may be triggered. a line reversal can be quali fied by determining if the change in polarity is stable for 50 to 100 ms. line activity the lact detector can be programmed to drive the linestat interrupt pin. this avoids the need fo r continuous polling of either the lp (line polarity) or rng (ring detection) bit. lact detects 10 to 20 v changes in either direction, also triggering on any ring, l ine reversal, or hook status change. when a linestat interrupt occurs, the sy stem would poll the rng, lp, and liu bits and apply qualificatio n algorithms for about 100 ms or until line activity stops.
ia3222/ia3223 32 line in use and line disconnect the liu detector is a dc line-voltage thre shold detector. one of four levels (~2.5, 15, 22.5, and 30v) can be selected. unfortu nately, line-in-use status is ambiguous for voltages between 12v and 19v . central office lines and short-range digital loop carrier sys tems always provide at least 21v of on-hook voltage. some pbxs and voip boxes may supply less. telephone devices will generally work with less than 12v at a loop current of 20-30ma. users sometimes a dd in-line zener devices (a vailable at radio shack ? ) in series with answering machines in order to improve parallel-pickup di sconnect performance. these in-line zener devices increase the answering machine?s off hook voltage by 6 to 8v, often pushing the total off-hook vo ltage above 15v. on short loops with 60ma capability, some telephone device s may drop over 12v when off hook. european te lephone devices with ctr-21 current limiting may even exceed 32v when off hook on short lines, especially in france. for most situations, the 15v liu threshold setting should be the default. a simple technique to reduce ambiguity is to use both liu and snoop audio detection. a more sophisticated method is to have the system learn normal on and off hook voltages by stepping through the liu levels of 15, 22.5 and 30v wh ile using the snoop circuit to monitor audio. the 2.5v threshold setting is intended to differentiate a discon nected line (not plugged in) from a powered line without attemp ting to distinguish on hook from off hook. a disconnected line may create erratic 2.5v and li ne-reversal detection. th is is because the line side has over 5 m ? input resistance. less than 100 na of on-hook loop curre nt can trigger the 2.5v thre shold. this behavior is similar to putting a standard 10 m ? input voltmeter on a long open line and seeing several volts due to static or leakage. generally, a valid line is present only if the voltage is stable above 3v and not reversing. if it is below 2v or reversing, the line shou ld be considered disconnected. off-hook loop-curre nt reversal (if available on a trunk) occurs only after dialing to indicate far par ty answer (toll call). the linestat pin as interrupt (on hook) the linestat pin is an active-low interrupt output. because it has an open-drain output with a weak internal pull-up resistor, it can be wire-ored with other interrupts in the system. when linestat is active, the system must determine the cause of the interrupt ba sed on history and the state of the daa. the ta ble below suggests criteria for qualifying the interrupt when the daa is on hook: lsr required setting possible cause of interrupt criterion high ringing expected ring cadence both at linestat pin and at rng bit line reversal lp bit changed compared to before interrupt, stable for 100 ms line in use liu bit high if prev iously low, stable for 100 ms line no longer in use liu bit low if previously high, stable for 100 ms low line activity no ring cadence or change in lp or liu bits audio snooping the snoop circuit does not have the same audio performance as th e off-hook receiver path, but it is adequate for caller id deco ding and line monitoring. snoop audio recovers from all high voltage line signals in less than 10 ms and is continuously present. be sides caller id, snooping can be used to monitor the line for call loggi ng or used for voice/fax steering. if a fax calling tone or a specific dtmf sequence is detected, the daa may be instructed to seize th e line. since dtmf signals normal ly have higher amplitude than caller id signals, a -6 db gain setting exists for the snoop path (sgain set to zero), which allows monitoring of up to 4 vpp s ignals without clipping. theory of operation? off-hook line status in the off-hook state, the same gyrator circuit that is used fo r on-hook line-status monitoring is reconfigured to filter audio signals from the line-current change circuit (parallel-pickup detector), so that changes in loop current can be measured without spurio us parallel-pickup signals from normal audio. capacitor cext2 with an internal 1.2 m ? resistor forms large time constant that stores the average dc value of the received signal. this dc value is compar ed with short-term changes to de tect loop current drops caused by a parallel phone on the line going off hook. sensitivity to parall el pickup is also affected by the ia3222 line-side?s holding an d ac-input capacitor values. there are four levels of parallel-pickup sensitivity, programmed by register bits lth0 and lth1. each setting is about twice as sensitive as the previous. when a parallel-pickup event occurs it causes a temporary active state both at the pp u (parallel pick up) bit and at the linestat pin.
ia3222/ia3223 33 line drop line drop or wink is a complete drop in loop current from the central office switch, usually indicating call disconnect or call waiting depending on the duration of the drop. dr ops over 500 ms indicate disconnect whil e shorter drops indicate call waiting. consequently, it is important to time the duration of line drops with at least 10 ms resolution. line drop is detected by the i a3223 system side and flagged as the ld (line dr op) status bit when the ia3222 line side rece ives insufficient loop current to keep i t operational (less than 10 ma). parallel pickup generally, the primary reason for parallel-pickup detection is to allow automatic telephone devices (set-top box modems, fax machines, etc.) to drop the line if a para llel telephone device attempts to dial. wh en a parallel telephone device goes off hoo k, the loop current into the ia3222 line side decreases. the parallel-pi ckup circuit detects the low-fr equency (less than 100hz) trans ients associated with a parallel pickup or hang up. to prevent spurio us detects due to large, low fr equency audio signals, the parall el- pickup circuit attenuates audio-band signals. at the most se nsitive setting, the parallel-pickup circuit will spuriously detect maximum amplitude voice and dtmf signals but not modem signals. parallel pi ckup di/dt may be very low either because the parallel phone has a high off hook voltage relative to line side ic or beca use the parallel phone holding ci rcuit (electronic inductor) may tu rn on slowly. the parallel-pickup circuit mu st therefore be very sensitive. in a modem or fax application, lower parallel-pickup sensitivity can be set when dialing dtmf tones to prevent a spurious detec tion. a higher sensitivity can then be set afte r dialing. typically, a -10 dbm modem signal transmitted from the daa will not trigger the parallel-pickup detector on its most sensitive setting. one method for setting the levels is to raise the sensitivity until spu rious detects occur and then reducing the sensitivity by one step. each step has about a 6db difference in sensitivity. because the transmit-to-receive trans-hybrid return loss is poor at frequencies below 100 hz, it is important that there be no low- frequency transients in the transmitted audi o signal, so as to prevent spurious parallel-pickup detections. modem software can create low-frequency settling transients wh en switching modes, typically during training or dtmf dialing. these may cause spuri ous parallel-pickup detections. if adjusting the modem software is no t possible, another solution is to put a low-frequency blockin g capacitor in the transmit path. the linestat pin as interrupt (off hook) in the off-hook state, the linestat pin be haves in a way similar to the on-hook state. the table below suggests criteria for qu alifying the interrupt when the daa is off hook: lsr required setting possible cause of interrupt criterion line drop ld bit high loop-current reversal lp bit changed compared to before interrupt high parallel pickup ppu bit high
ia3222/ia3223 34 measuring loop-current changes th rough the received audio signal the line side senses line-current information and encodes it for the system side as a dc offset superimposed onto the received audio data. since modem dsp algorithms routinely remove low-freque ncy components from the incoming data stream, dc offset is not a problem, but it needs to be taken into account in headroom calculations. the current sensor has considerable dc offset, which needs to be calibrated to obtain good current-sensor performance. this is achieved by adding a dc component to the transmitted data proportional to the receiv ed dc offset using the following algorithm: ? disable the current sensor by setting bit lp1 in the line-side lsb programming regist er. this cancels the dc component due to the loop current itself and leaves the current sensor?s offs et component as dc offset in the received data stream. ? add a small amount (20 to 50mv) of dc offset to the outgoing data and note the amount of change in dc offset in the incoming data. the ratio of incoming to outgoing dc offset changes is the dc-offset correction factor, for which the sign must be retain ed. ? add a dc offset to all transmitted data eq ual to the received dc offset divided by the dc-offset correction factor, based on th e desired dc reference for the received signal. this is normally the same voltage as that of the acref pin. ? enable the current sensor. the loop current can now be read as incoming-data dc offset from the dc reference voltage. the sensitivity of the current sensor is approximately 1.25 mv of dc offset for every 1 ma of loop current. note that both the dc-o ffset correction factor and the gain change with the line-side termination impedance setting.
ia3222/ia3223 35 surges, isolation and emc among the three regulatory domains that daas must comply with (telecom, safety and emc), safety and emc tend to be highly intertwined. designing for regula tory approval can sometimes compromise field re liability of daas. historically, the dominant c ause for field failures of modems or other daa-based telephone produc ts has been electrical overstre ss from the telephone line, typi cally due to lightning, esd, or incompatibility with digital pbx lines. the most common failures are both metallic (differential) and longitudinal (common mode). metallic failures are evidenced by damage to components on the line side while longitudinal isolati on failures usually damage the drivers or rece ivers on either side of the isolation barrier. overdesigning for surge immunity is n ot uncommon with daas. this can add as much as a dollar in costly surge components compar ed to what is necessary to pass required regulatory testing or field stresses, which are often poorly understood. even minimal surge and regulatory isolation components may be the most expensive non-ic components in the daa bill of materials. moreover, contrary to expectation, more robust surge components may actually make the daa less robust overall. for regulatory, functional and safety reason s, daas provide isolation and protection against excessive voltages and currents. t he telephone line system provides dc and ac common-mode grou nd at the current-source end of the line. at the user end or cpe (customer premise end), the telephone device must be insulated either inherently or using a daa. the classic example of inherent isolation is the standard tele phone, which is not connected to the ac mains. but commonly, answering machines and cordless telephones also are completely in sulated despite being powered by the mains. in these products, two-prong transformer wall supplies provide the safety isolation. products that ha ve a third prong safety ground on the power p lug almost always use a daa for the loop interface. if a product ha s a conductive chassis or has other electrical connections, it u sually will need a daa to interface to the telephone line. examples in this group are alarm systems, set-top boxes, fax machines, remo te meter readers, etc. functionally, longitudinal isolation at the cpe is the optimum solution for achieving very high common-mode noise rejection. repetitive longitudinal transients on the telephone line twiste d pair may exceed 10v peak and continuous ac may exceed 70 v rms (+40 dbm). since the basic audible noise floor is around ?75 dbm, this is over 110 db of dynamic range. only dielectric isolati on provides both very large common-mode range withou t overload and excellent common-mode rejection. as in medical instrumentation systems, dielectric isolation, be sides providing high common-mode immunity, also provides safety isolation against electrical shock, overstress damage and fire. generally, these latter issues are the concern of regulatory sa fety standards. in many markets, the telephone line in terface must satisfy these requirements strictly. consequently, daas provide a unique challeng e in consumer products, needing to meet industrial isolation and robustness but at consumer prices, unlike the industrial slic (subscriber line interface circuit) on the other end of the phone line. traditional ly, slics are part of the total cost of the local telephone line that ma y have a capital value of $1000 that is amortized over a forty-ye ar life. for every industrial slic sold, there may be twenty consumer telephone devices sold. safety isolation and differential surges the sources of safety or damage causing el ectrical stress are lightning-induced transi ents, esd (electrostatic discharge), ac p ower- line crosses, ac power line transients, an d incompatibility with digital pbx phone powe r. proper daa design can eliminate these hazards. lightning-induced transients and es d are very similar in behavior and the damage th ey cause. generally, the best remedies for o ne work well for the other. lightning transients come down the tele phone line from outside while es d transients occur on cpe side. lightning rarely strikes the phone line directly, but more commonly couples into the telephone line via several different mecha nisms. one is that it strikes the high-voltage di stribution lines on the same pole as the phone line. the strike may deliver a brief 1 ka pulse down a hundred meters or more of power line before arcing to ground through the nearest power- distribution lightning arrestor. since the strike current runs parallel to the telephone lines, it s very high di/dt induces a large common-mode voltage in the p arallel phone cable. for example, if the lightning strike delivers 100 a/ s di/dt (1 ka over a 10 s rise time) down a 100 h power-lin e inductance (say a 100 m power line at 1 h/m), this generates a 10 kv inductive voltage down the power line. if the phone cable is relatively close (e.g. 10 m) to the power line compared to the coupling length (e.g. 100 m), then a large percentage of this in ductive voltage will couple to the twisted pairs in the telephone cable below. although the twisted-pair phone cable has a conductive s heath around it that is grounded periodically an d that acts as an eddy-current shield, its efficacy is limited by its own return indu ctance and resistance through the ground path, which is often even further aw ay than the inducing power lines. in other words, the power l ines and the telephone cable form a very low impedance pulse transforme r that may couple to the telephone line up to 30 or 50 % of t he
ia3222/ia3223 36 lightning voltage drop down the power line. the net effect is that several kv of longitudinal transients can be put on the tele phone line for any lightning strike on the power line that runs abov e the same telephone lines. since the phone line may run for seve ral miles, it may not be unlikely that a strike abov e it happens several time s every lightning season. another coupling method for lightning is vi a ground-return bounce. since the lightning st rike must return to ground and especia lly if the ground is resistive, the loca l voltage at the ground return may bounce by th ousands of volts for several tens of microsecon ds. if the local ground is at the switch end of the telephone line, of course this will induce a comm on-mode transient toward the cpe end of several kv. conversely, if the strike ground return is local to the cpe, it will make the local ground bounce by several kv relative to the telephone switch end that may be miles away. either mechan ism generates a longitudinal transient between the telephone line and the local ground of several kv. lightning is not the only source of such transients. the powe r-distribution system can also generate common-mode induction transients through the same coupling mechanism. these transients may arise from power-distributi on switching or heavy-duty load s (industrial motors, etc.). genera lly, these induction even ts are rare, and are mostly a source of common-mode noise, not produc ing voltages high enough to cause damage. these transients are the reason why telephone lines all have primary lightning arrestors to local ground at the pstn (public sw itched telephone network) network access port. normal ly, there is one primary arrestor on each side of the telephone line to a local ground, typically a clamp on a water pipe or ground stake. these arrestors trigger in the 300 to 600 v range. common arrestors have been 6-mil carbon gaps, gas tubes, movs (metal oxide varistors) , or semiconductor breakover diodes. the carbon gaps and gas-tub e arrestors are slow and may take several s to trigger, allowing up to several kv for a few s. typically, the arrestors can wit hstand at least a 100 a surge for a standard lightning surge pulse of several hundred s. the resi stance of the telephone line limits the current. typical 26-gauge twisted-pa ir cable has a resistance of 40 ? per kft. surge suppressors either have breakover characteristics where their forward voltages drop to a few volts when triggered but need at least 100 ma to keep them conductiv e, or have zener voltage clamp characteristics. voltage clamps (movs ar e the common example) need to be able to absorb many joules of energy without damage (1 kv x 100 a x 100 s = 10 j). with th e breakover diode, the peak current may be several times higher because it provides little blocking voltag e, but it dissipates less than 1/100th of th e energy of voltage clamp because of its low forward voltage. the bulk of the surge energy is dissipa ted down the series resistance of the telephone line. if the primary arrestors always were in place and properly ground ed, then much of the observed lightning damage to daas would n ot occur. unfortunately, over the life of telephone line, a number of ground connections at the network-access point may get disconnected due to building construction. the ground is often not reconnected because the telephone line works fine without it . the surge arrestors may also be damaged and not replaced, or the network-access port is removed and not replaced. even a properly installed ground stake in a desert climate may fail if the soil dries out, thus causing a high-impedance return path to ground. arcing across the isolation barrier is the more serious daa failur e that arises when the primary arrestor protection is defecti ve. longitudinal voltages need to rise above 2 to 3 kv before arci ng occurs. lower voltages usually don?t arc since most daas are designed to withstand transients of at least 1.5 kv and the continuous application of 1 kv rms . even though longitudinal transients above 5 kv may be rare, electrostatic (esd) transients can easily exceed 10 or 15 kv. a telephone product that includes a daa m ight be struck by an esd event and not have an adequate ground return. the resulting esd event may then arc across the isolation barrier. for example, a user might be installing a fax machine at home and then plug the telephone line before plugging the pow er cord. if an esd transient strikes while the fax machine is unpl ugged, then the daa might be da maged due to arcing across its isolation. there are several remedies for the esd event. one is the use of common-mode, high voltage emi capacitors between the chassis ground and the phone line. these are typica lly installed for reduction of emi radiatio n and susceptibility. if each of these is around 470 pf, they will divide the voltage of an esd transient by as mu ch as ten times. since these capacitors must meet the telephon e- line isolation requirements, they will na turally withstand the divided voltage. the ia3222/3223 chipset does not need these costly emi capacitors because of the high rf impedance of the isolation capacitors. these capacitors achieve an effective breakdow n voltage in the tens of kv at only the cost of the pcb area they occupy. in prac tice, excessive common-mode voltage will arc across the surface of the bo ard. if the daa designer doesn?t select a preferred path for common-mode arcing, the surge will find its own path with conseq uent damage. a preferred arc pa th would normally be between either tip or ring and the chassis ground of the telephone produc t. the desired arc gap should be both shorter and more pointed than any other potential arc path. if part of the arc gap is on the circuit board it is important that the ends not have insula ting silkscreen over them. for most worldwide applications, the gap should be at least 2.5 mm. this means that the other creepage (surface distance) distances should be at least 3 mm.
ia3222/ia3223 37 metallic (differential) surges arise from the longitudinal lightn ing surges causing either the asymmetric triggering of the pri mary arrestors, or arcing of only one side of the line to ground (if only one primary arre stor is functioning). to protect against m etallic surges, a daa uses a surge suppressor that clamps the different ial voltage to prevent damage. good solutions provide surge immunity for both on-hook and off-hook daa states. protecting the off-hook state requir es some form of current limiting to prot ect the off-hook path during the surge. breako ver diodes generally work better since they collapse the surge voltage, thus reducing the energy dissipated in the off-hook circuit ov er 100 times. movs can be used for surges , but because of their nearly two-to-one s pread between minimum and maximum clamp voltages, the hook switch must be capable of withstanding much higher peak voltages than with breakover diodes. in addition, the hook circuit must turn itself off (bla nking) during the surge in order to prevent exces s dissipation. because the primary arrestors are not typically in a mutually tri ggered pair (unlike some gas tubes) during a common mode high voltage transient, one arrestor will always fire before the other. ironically, on a telephone product with a breakover secondar y surge protection diode between tip & ring, this ca n lead to overstress of this diode especial ly if the primary arrestors have a break over characteristic (carbon gap, gas tube, or se miconductor breakover diode). the reason is that once a primary arrestor triggers on one side of the line, the longitudinal surge becomes metallic. this triggers the secondary breakover diode in the telephone product . at that point the other primary arrestor won?t trigger at all, since there is now a low-vo ltage path around it through the seconda ry protector and back though the first primary protector that fired. in this situation, the breakover diode sees the same current as the primary arrestor. typically, for this mechan ism to occur both primary and secondary su rge protectors need to have break-over characteristics. there are several remedies to prevent this. one is to insert a resistance of about 5 ? in series with tip and ring but before the breakover diode. the added resist ance increases the voltage drop sufficiently to ensure that the second primary arrestor trigge rs on large current transients. small tran sients can be absorbed by the breakover diode. if a resistor is used, it must be capable of withstanding the worse-case surge. if it ha s suitable fuse characteristics and is flam e proof, then it can be used as an inexpe nsive slow-blow fuse for protection against line cross. contact silicon labs for possible resistor types. another remedy is to use a larger secondary breakover diode. what surge capacity, then, does a breakover diode need to withstand for low field return rates? experience shows that a daa tha t survives an fcc part 68 type-b surge provides good field immunity against most lightning surges over the life of the product. t his surge specifies a 1 kv peak produced by discharging a 20 f source capacitor with about 40 ? of resistance for limiting current. into a break-over diode, this produces a peak current of about 25a. several vendors pr oduce breakover diodes rated to survive this t est. although the designer can use more robust components to surviv e a fcc part 68 type-a surge, (800v, 100a), the added expense is probably not warranted. furthermore, a type-a surge only requires a safe failure mode, not continued product operation. general ly, lightning surges that produce differential su rges of 100a are likely to cause extensive damage to a wide variety of electrical devices in the house. as pointed out earlier, the telephone line resistance limits the peak current. long lines will tend to have highe r-voltage and more numerous surges, but the increased resistance helps limit the surge current. the ia3222 line side has a smart power-limiting hook control circuit that prevents damage to the hook switch; either during hig h voltage surges or even if continuous high voltage is present on the line. the chip se nses both line voltage and line current. i f the line voltage exceeds 100v or the loop current exceeds 170ma, the hook switch turns off to prevent exce ssive power dissipation in the main hook transistors. this prevents ther mal overstress damage as might occur during ringing peaks, from any surge voltage, or by connecting the daa to a digital pbx supply with no current limit. the digital pbx issue has been a major retu rn rate problem on modem daas especially for laptop computers. digital pbx phone systems normally provide 24 to 50v to power smart phones. this power may be current limited to 1a or even more, only to prevent a fire hazard. some systems provide power, control and audio digital signaling down the normal tip and ring pair. if a regular telephone device is plugged into these lines, it may damage the daa, since normal daas only expect up to 120 ma of loop current . power-line cross a power-line cross happens when a power line erroneously gets connected to the phone line. all daas provide isolation protectio n against common-mode power line cross, but may not provide protec tion against differential line cross (full power applied betwee n tip and ring). most regulatory standards only require protection ag ainst common-mode power-line ac voltages and not differential po wer line voltages. line cross is a much rarer event than lightning surges. over the life of the product, this typically has less th an a 1% chance of happening. a line cross can occur from the user side or from the telephon e system side. if the chassis of a telephone product somehow gets shorted to one side of the ac power line, then the daa isolat ion protects telephone-company technicians and equipment from
ia3222/ia3223 38 excessive voltages and power. from the tele phone system side, a line cross might occur if a power line falls across the telepho ne line shorting to one side of the line. power-line cross is diffe rent than lightning surges because of its longer duration. this makes it much more dangerous even though it is less likely than lightnin g surges. failure can occur either from isolation breakdown or f rom consequent excessive voltage between tip and ring , which can create a fire hazard in the daa. a power-line cross may start out as a longitudinal high-voltage event but may quickly turn into a metallic event. when a power line gets connected to one side or the other of the telephone line, it may cause the primary surge suppressor to trigger, which in t urn burns open, leaving the ac mains on one side of the phone line. then, either if the te lephone device goes off hook, or if the breakover diode triggers, the other primary arrestor may trigger, creating a path directly through the daa for the ac power lin e. in this scenario, there may be very little telephon e line resistance in the current loop (less than 50 m of line) to limit the current. the result is a destructive failure of the daa. it may burst into flames du e to continuous pouring of energy into the daa surge suppressor , which is normally not capable of continuous currents above 1a. safe differential line-crossing fail ure, when required, only means that the product needs to fail safely on a line cross, i.e. not burst into flames during the test. designing a daa to survive a line cross is possible but at a significant cost. the simple method i s to use an expensive 600 v ac ptc (positive temperature co efficient) resetable fuse. if the daa needs to provide safe differential line-crossing failure, the normal solution is to have some type of slow fusible l ink. fast- blow fuses will likely get blown by lightning transients and ar e therefore not recommended. there also exist special (and costl y) telecom fuses that will survive a 25a peak type b surge but will bl ow on a differential line cro ss event. another solution is t o use a 5 to 10 ? , 1 to 2 w, flame-proof metal-oxide resistor for a fusible link. with some testing and care, this cheaper solution will withsta nd the type b surge but safely blow on a line -crossing event. (contact si licon labs for possible resistor types.) this also has th e advantage of limiting the surge current that results from asymme trical firing of the primary lightning arrestors. any fusible l ink needs to be flame proof and physically separate from the pc board, si nce the ul 1459 test ramps the ac voltage slowly up to 600 v ac to allow components to generate heat and possibly start a fire, rather than just blow apart. if a component such as a metal oxide resistor begins to glow and is lying flat on the pc board, it will carbonize the pc board material, which may lead to conductiv e tracking (carbonized insulator becomi ng conductive) and possibly fire. common-mode noise from the mains supply a hidden common-mode noise issue arises from the absence of the third (green) wire safety ground in home ac power wiring. in th e us, third-wire grounds and three-prong ac outlets were not installed extensively unti l the mid-1950?s and were not required by code until the early 1960?s. europe and other coun tries have similar hi stories. thus in older homes th ird-wire grounds are missing i n some or all rooms, even if three-prong sockets are present. when computer equipment with switching supplies is plugged into such an outlet, up to half of the ac mains voltage can be measured on the chassis ground relative to real earth ground (or the telephon e) line. the reason is that most computer switching supplies have pi network power-line emi filters that have rf decoupling capaci tors in the nf range tied between live, neutral and ground. if the thir d-wire ground is not actually grounded, the capacitors in the filter create a divider between li ve and neutral with the third-wire ground. it is possible to get a slight electrical shock from a co mputer chassis just from this effect. more significantly, it creates a very large common-mode noise vo ltage between the phone line (in effect a ground connection) and the local, ungrounded ground wiring. this large ac common-mode voltage sometime s causes overload problems on resistor-c apacitor isolated caller id circuits. the iai3222 does not have this issue since it is completely isolated. even with otherwise isolated daas, emi immunity capacitors, i f mismatched, can introduce noise on the telephone line, especially if large ac line transients ar e present. for example, if two 470 pf emi capacitors are mismatched by 5%, the 23. 5 pf unbalance has an impedance of 2.3 m ? at 3 khz. against a typical line impedance of 600 ? , this represents 72 db of common-mode balance. if the power line has 20 v audio-band transients and the third wire ground is disconnected, this results in 10v at the chassi s and will inject about 2.6 mv of audio noise on the phone line, enough to disrupt most high-speed (v.90, v.34, v.32) modem communication. for this reason, emi bypass capacitors, when they are necessary, should be of the lowest value necessary to reduce emi to the desired level. worse yet, some capacitively-coupled daas use more than 60 pf of signal-isolation capacitance that is not balanced relative to tip and ring. even without emi capacitors, significant noise can be inje cted into the line if the system third-wire ground is float ing. similarly, base-band linear opto-isolated daas can inject line noise even though the capacitive coupling across the isolation b arrier may be less than 1 pf. the reason is that opto-isolated systems need a gain of almost 100 on the transfer and servo photodiodes because of the typical 1 % current-transfer ratio. normally, there is a small amount of isolation capacitance in the sensitive servo or transfer photodiode to the effect that at 3 khz the common-mode balance may be 80db or less.
ia3222/ia3223 39 emc another key advantage of the ia3222/3223 chipset is that many applications do not require the usual telephone-line emc suppression components. the 2 pf total value of the isolation ca pacitors presents significant impedance at vhf and uhf radiatin g frequencies. at 300 mhz, 2 pf has a reactive impedance of 265 oh ms? comparable to that of ferrite beads. this coupling impedance is significantly higher than other capacitor daas where the isolation impedances can be ten times lower or even less. compared to these other daas, the chipset will couple better than 20 db less rf to the phone line if no other rf suppression is used and will be comparable to the other capacitor-coupled daas where ferrite beads are used. if higher levels of rf suppression are required, adding emi shun t capacitors between each side of the line to the chassis will be more effective than adding ferrite beads. to minimize the need for e mi shunt capacitors, the line side area (antenna) should be mini mized and placed as close as possible to the phone line connector. exte nding the chassis ground on each of line side (while still maintaining minimum isolation creepage) will act as an rf shield. if board area is available, the emi line capacitors can be fa bricated like the pcb isolation capacitors by using the upper and lower pcb layers. matched 10 pf capacitors on each side of the line to the chassis would attenuate line rf by about 20 db. rf susceptibility for daas, large common-mode rf signals below 2 mhz can be a se rious source of interference. in particular, am radio-band transmitters in the 500 khz to 1.6 mhz range are common in urban ar eas. although the field strength for am radio is typically n o more than other urban signals (tv, fm, two- way radio, cell phones, etc.), the twisted-pair telephone line from the pole plus th e unshielded telephone line in the building makes an excellent lo ng-wave antenna since neither of these are shielded like the mul ti- pair cable on the pole. because of the long wavelengths in this band (150 to 600 m), a quarter-wave long wire antenna has a lar ge rf capture area, providing up to a hund red times higher common-mode signal leve ls than the field strength per meter. consequently, it is not unusual to see many volts of common-mode rf signal on the telephone line. this can easily be seen by putting an oscilloscope probe on tip or ring . to prevent interference from these am-ban d signals, some daas require both expens ive series inductors in the range of severa l h and high-voltage shunt capacitors. without the need for these costly rf suppression componen ts, the ia3222/3223 chipset achieves very high common-mode rf immunity. this results from the combination of very low isolation capacitance and internal filtering. typically, rf immunity of the ia3222/3223 will be sufficient and the daa will perform quite well without any special rf suppressi on components. on the other hand, if immunity is desired to the level specified in en 55024 or even to brazil?s more demanding anexo a resolu??o no 237, a pair of 470 pf high-voltage capacitors be tween tip/ring and the chassis ground is no rmally sufficient. in general, filtering components work both ways: any rf solution that works well for radiated signals will work well for susceptibility in the same frequency range.
ia3222/ia3223 40 return loss and trans- hybrid return loss telephone devices transmit and receive bi-directionally down a tw isted-pair line. all of the tran smitted signal would be presen t on the receiver were it not for a cancellation circuit called hybrid or two-to-four-wire hybrid. a hybrid works by canceling the actua l echo back from the line with the expected transmitte d reflection. the expected reflection is de termined by applying the transmitted signa l through an analog of the driver impedance applied across an anal og of the line impedance (also called a ?line mirror? short for ?line- mirrored impedance? or ?balance network?). if the actual line impedance and drive impedance is identical or balanced perfectly by the line mirror and mirror drive impedance, then the echo canc ellation will be complete. in practice, the impedance varies significantly with the length of the line and with the presence of bridged taps (parallel open-circuit twisted pair stubs), so that echo cancellation varies with th e frequency of the transmitte d signal and with the line. the standard measure of the cancellation of the hybrid balance is return loss. this is a measure of the reflection from the tra nsmit path back to the receive path in terms of loss (attenuation) no rmalized to levels on the telephone line and expressed in db. th e higher the loss, the lower the reflection and the better the hybr id balance. for example, a 20 db return loss at a given freque ncy indicates that the transmitted signal at the receiver will be 20 db lower than if the same level of signal was received on the telephone line from an outside source. return loss for a line and its terminating impedance can also be calculated if both impedances are known. hybrids are normally present both at the sl ic or switch end and at the cpe or loop termination end. confusion sometimes arises since return loss is used to measure both the accuracy of the impedance termination on either end of the phone line and also to measure the efficacy of the hybrid in cancelling the reflection. this latter is called trans-hybrid or four-wire return loss. t he return-loss figure on the termination impedance indicates the reflected si gnal amplitude due to the impedance mismatch from an ideal termination. many telephone line interfaces, whether slic or daa, may provid e several levels of hybrid balancing. commonly, a first-order an alog compromise line mirror is used, which may provide only about 10 db of balance over a range of telephone lines. its purpose is t o reduce the dynamic range of the receiver channel (or codec) by this amount since telephone systems require about 80 db of dynamic range. if the application requires better hybrid balancing, then some form of dynamic or line calibration is required. the degree of total hybrid balancing needed is a function of the telephone application. the main purpose of central office or e nd office hybrid balancing is to reduce far-end voice echoes that can be very annoying and degrade the quality of service. surface communication paths (optical fibe r, coax, etc.) round-trip echoes between the no rth american west coast and europe can approach 200ms. on a new line installation, the hybrid mirror at the centra l office requires tuning at le ast for loaded ve rsus non-loade d lines. telephone-network echo cancellers dynamically adjust hybrid balance, but in order to work best require some minimum compromise hybrid balance. central office hybrid tuning assumes that the telephone line is terminated with a standard impedance. for most of the world this is 600 ? . in some countries, the 600 ? impedance is replaced with an rc network that better approximates the complex impedance of a long non-loaded telephone line. this redu ces hybrid-balancing differences between short and long lines. in practice, the return-loss matching of the terminating impedanc e is not very critical for two reasons. first, the bi-directio nal loss down a typical telephone line reduces the effects of any 600 ? or complex impedance mismatch by twice the nominal loss. for example, since the average telephone line lo ss is about 4db, on such a line the effects of a termination mismatch on the centra l office slic hybrid balance will be reduce d by 8 db (the attenuation in each direction). secondly, the line-length variation of the return loss is the dominant effect, swamping most production terminat ion impedance variations. for exam ple, a median-length telephone line of 5,000 ft has an added 400 ? of series resistance and a di stributed capacitance of around 80 nf. since most speech audio is below 1 khz, the telephone-line resistance has the dominant effect on echo that is not mitigated much by the distributed capacitance. evidence that termination impedance variation is no t critical is suggested by very wide margins on return loss requirements in mainstream regulatory approval. us fcc part 68 has no return-loss impedance requirement, that of tbr21 is very low (only 8 db) and jate requires only a few db. on the cpe side of the telephone line, there is no regulatory requirement for trans-hybrid return loss, but that parameter has a more significant functional impact on mo dem performance or audio quality. all high-speed full-duplex modems (v.32, v.34, v.90 and v.92) during training build an exact line mirror (of what is left over from the daa compromise hybrid) to cancel the echo to better than 70 db. the ia3222 has a compromise tr ans-hybrid balance network on the line side that improves the dynamic range performance of the analog channel by minimizing the transmitted noise and distortion reflected back into the receiver channel. both of th ese are very critical for high-s peed modems. a hidden critical e lement for high-speed modems is hybrid thermal drift. if the hybrid retu rn loss, transmitter or receiver gain drifts by even a small a mount (less than -60 db) between initial training and several minutes later, the modem performance can be greatly degraded since the un-
ia3222/ia3223 41 cancelled residual is seen as noise. trans-hybrid drift mostly arises from thermal effects due to heating of the line side both from the line current and the electronic environm ent. the ia3222 was designed to have very low thermal drift to minimize these effec ts. in telephony applications, hybrid return loss is heard as ?sideton e?. some sidetone is desirable as long as it is not excessive in volume. the ia3222 hybrid network, like most telephones, provides a good compromise si detone over most normal loaded and non- loaded lines without requiring other compensation networks. better trans-hybrid balance against any line can be achieved by adding a suitable analog or digital transform between the transmitted audio and the received signal summing node. this can be done in the analog domain with rc networks, some type of receiver summing node (either resistive or using an op amp) and some type of transmitter inversion. similarly, different termination impedances can by synthesized either in the analog or digital domain by complex transformation of the receiver signal back into the transmitter input. in some di gital daas, the sampling delay prev ents this except for very low frequencies. but since the ia3222/3223 uses ei ght-times oversampling, line to rx pin an d tx pin to line delays are significantl y less, thus making impedance synthesis possible.
ia3222/ia3223 42 package information qsop-16 and qsop-20 packages msop-10 package soic-8 package (jedec outline ms-012aa)
ia3222/ia3223 43 ordering information ia3222/ia3223 daa chipset with analog interface description ordering number ia3222a ? line side us/japan daa ic ia3222a-ic cb8 ia3222b ? line side enhanced worldwide daa ic ia3222b-ic cd10 ia3223 ? system side worldwide daa ic ia3223-ic ci16 ia3223a ? system side worldwide daa ic with pin hook control ia3223a-ic ci20 silicon labs, inc. 400 west cesar chavez austin, texas 78701 tel: 512.416.8500 fax: 512.416.9669 toll free: 877.444.3032 www.silabs.com/integration sidaainfo@silabs.com the specifications and descriptions in this document are based on information available at the time of publication and are subject to change without notice. silicon laboratories assumes no responsibility for errors or omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes to the product and its documentation at any time. silicon laboratories makes no representations, warranties, or guarant ees regarding the suitability of its products for any particular purpose and does not assume any liability arising out of the application or use of an y product or circuit, and specifically disclaims any and all liability for c onsequential or incidental damages arising out of use or failure of the product. nothing in this document shall operate as an express or implied license or i ndemnity under the intellectual property rights of silicon laboratories or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. no warranties of any kind, including but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document. ?2008 silicon laboratories, inc. all rights reserved. silicon laboratories is a trademark of silicon laboratories, inc. all other trademarks belong to their respective owners.

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